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| ( DataSheet : www..com ) Features * * * * * * * * * * * * Compatible with an Embedded 32-bit ARM7TDMITM Processor Up to 32 Programmable I/O Lines Interrupt Generation on Event Glitch Filter Fully Scan Testable (up to 98% Fault Coverage) Can be Directly Connected to the Atmel Implementation of the AMBATM Peripheral Bus (APB) of the ARM7TDMI Microcontroller Multi-driver (Open Drain) Option Certain Options "Parametrizable" on Request: Number of Programmable Lines Glitch Filter Option Multi-driver (Open Drain) Option Reset State of PIO Status and Glitch Filter Status Description The Parallel Input/Output 1 (PIO1) 32-bit embedded core peripheral features 32 fullyprogrammable input/output lines, each of which may be dedicated as general purpose I/O or be multiplexed with a signal generated by another embedded peripheral, in order to optimize the use of available package pins in the overall system-on-chip design. The PIO1 controller provides a bit-maskable event driven internal interrupt signal. The PIO1 and other analog and digital modular embedded peripherals, together with a choice of microprocessor and DSP cores, on-chip RAM, ROM, EEPROM and Flash memory, as well as special purpose analog or digital user-developed blocks, allow rapid and cost-effective design and implementation of an optimized system-on-chip. The large range of functional blocks offers a realistic and efficient design pathway to system-level integration (SLI). The PIO1 is bus-compatible with the ARM7TDMI 32-bit microcontroller core. It can also be used with other 32-bit MCU or DSP cores. The PIO1 is supplied with comprehensive test vector sets. Atmel's proprietary foundry interface tools ensure a smooth transition from design to fabrication. 32-bit Embedded Core Peripheral Parallel Input/Output 1 (PIO1) Rev. 1321C-03/01 1 www..com Figure 1. PIO1 Terminal Connections nreset Chip-wide nreset_f clock p_a [13:0] p_d_in [31:0] p_d_out[31:0] APB APB p_write p_stb p_stb_rising p_sel_PIO PIO_int Interrupt PIO1 Pad d_from_pad[31*:0] d_to_periph[31*:0] Peripheral d_from_periph[31*:0] d_to_pad[31*:0] oen_to_pad[31*:0] Peripheral en_periph_n[31*:0] Pad scan_test_mode Scan Test test_se test_si[2:1] test_so[2:1] Scan Test Note: *Depends on "On Request" parameters. For example, if 20 lines are requested, it will be [19:0]. 2 PIO1 1321C-03/01 PIO1 Table 1. PIO Terminal Description Name Function Type Chip-wide nreset nreset_f clock System reset System reset System clock Input Input Input Atmel Peripheral Bus (APB) p_a [13:0] Address bus Input - The address takes into account the 2 LSBs [1:0], but the PIO1 macrocell does not decode these bits From host (bridge) To host (bridge) From host (bridge) From host (bridge) From host (bridge)-Clock for all DFFs controlling the configuration registers From host (bridge) Low Low - Resets all counters and signals Clocked on rising edge of clock Resets all counters and signals Clocked on falling edge of clock System clock Active Level Comments p_d_in [31:0] p_d_out [31:0] p_write p_stb p_stb_rising p_sel_PIO Input data bus Output data bus Write enable Peripheral strobe User interface clock signal Selects the PIO1 block Pad Input Output Input Input Input Input - - High High - High d_from_pad [31 :0] d_to_pad [31 :0] oen_to_pad [311:0] 1 1 Pad input data Pad output data Pad output enable Input Output Output Peripheral - - Low Data from an I/O pad Data to an I/O pad Output enable for a bidirectional pad d_from_periph [31 :0] d_to_periph [31 :0] en_periph_n [311:0] 1 1 Peripheral data input Peripheral data output Peripheral data enable Input Output Input - - Low Data from an on-chip peripheral Data to an on-chip peripheral Enables data from an on-chip peripheral to a pad when a peripheral connection is enabled Interrupt PIO_int PIO1 generated Interrupt Output Test Scan scan_test_mode test_se test_si[2:1] test_so [2:1] Note: Clock selection for test purposes Scan test enable Scan test input Scan test output Input Input Input Output High High/Low High - Scan shift/scan capture Entry of scan chain Ouput of scan chain High Any I/O line may be programmed to generate an event driven interrupt 1. Depends on "On Request" parameters. For example, if 20 lines are requested, it will be [19:0]. 3 1321C-03/01 Figure 2. Interconnecting the PIO1 in an ARM(R)-based Microcontroller System-on-chip (Example) To Advanced Interrupt Controller (AIC) PIO_int USART Peripheral rxd txd en_clk_n d_to_periph d_from_periph en_periph_n Parallel Input/Output PIO d_from_pad nreset_f Chip-wide Signals clock clock nreset_f nreset nreset oen_to_pad d_to_pad Pad 32-bit Processor Core (ARM) Atmel Peripheral Bus APB Advanced System Bus ASB Atmel Bridge 4 PIO1 1321C-03/01 p_d_out[31:0] p_d_in[31:0] p_a[13:0] p_stb_rising p_sel_PIO p_write p_stb PIO1 Functional Description The 32-bit PIO1 peripheral is fully compatible with an embedded ARM7TDMI processor. The PIO peripheral features 32 fully-programmable I/O lines, each of which may be multiplexed with an on-chip peripheral signal. The device can also provide a bit-maskable event driven on-chip interrupt signal. The PIO1 peripheral is fully-controllable via five sets of three 32-bit registers; pin data and interrupt source conditions are available to user software via two 32-bit registers.Figure 3 illustrates PIO1 functionality and the effect of register programming as described in the following sections Figure 3. .PIO1 Control and Status Register Architecture PIO_OSR 1 Pad Output Enable 0 1 PIO_PSR PIO_ODSR PIO_MDSR Pad Output Pad 0 Peripheral Output Enable 0 1 1 0 Peripheral Output Pad Input PIO_MDSR 0 1 Filter 1 0 PIO_PSR Peripheral Input PIO_IFSR PIO_PDSR Event Detection PIO_ISR PIO_IMR PIOIRQ 5 1321C-03/01 Scan Test Configuration Fault coverage is maximized when all non-scan inputs can be controlled and when all non-scan outputs can be monitored. In order to achieve this, it is preferable that the ATPG vectors be generated on the entire circuit which includes the PIO1 embedded peripheral (top-level); alternatively, all of the inputs and outputs of the PIO1 should be made accessible so that ATPG vectors can be applied to all terminals. Each individual I/O channel is associated with a bit in the various 32-bit PIO user interface registers (control and status registers) which are listed in Table 2. The interrelationship of functionality with the various status and control registers is also illustrated in Figure 3. If a parallel I/O line is not defined, writing to the corresponding bits has no effect; reading the bit will return zero. Functionality of the PIO1 is governed by four 32-bit read-only status registers and a read-only interrupt mask register. These registers are each controlled by a pair of user software accessible write-only control registers. Two further read-only 32-bit status registers allow pin data and interrupt source conditions to be monitored by user software. When writing to a Control Register, only a logic 1 affects the related bit: thus, the user software writes a 1 to the Enable Control Register to enable the desired function, and it writes a 1 to the associated Disable Control Register to disable the function. Writing a logic 0 to a Control Register has no effect. Any attempt at writing to a read-only register has no effect. Any attempt at reading a write-only Control Register returns undefined data. Control Registers Bidirectional Multiplexed I/O After reset, all channels are connected to the PIO1 controller as I/O and are in input mode (unless the reset value of the related status registers is programmed otherwise during system design; this may be the case if other on-chip peripherals are connected to the outside world via the PIO1). I/O lines may be multiplexed with the input and output signals of another on-chip peripheral. The state of each bit of the PIO Status Register (PIO_PSR) determines whether the related channel is connected to an on-chip peripheral or as processor-addressable Parallel I/O. The PIO Status Register (PIO_PSR) is controlled by writing a logic 1 to the relevant bit of the PIO Enable (PIO_PER) or to the PIO Disable (PIO_PDR) Control Registers. Writing a 0 to a Control Register has no effect. When the PIO1 is selected, the peripheral input line is connected to zero. If a pin is a general-purpose parallel I/O pin (not multiplexed with a peripheral), PIO_PER and PIO_PDR has no effect and reading PIO_PSR returns a logic 1 for the bits corresponding to these pins. Output Enabling Each channel is effectively bidirectional. A channel output may be disabled by suitably programming the Output Status Register (PIO_OSR) via the PIO_ODR (Output Disable) write-only Control Register. Conversely, the user can enable a channel as an output by writing a logic 1 to the relevant bit of the PIO_OER (Output Enable) Control Register. The status of the various channels is monitored by reading the Output Status Register (PIO_OSR). Output enabling/disabling may only be controlled by user software when the channel has been configured as parallel I/O (via PIO Status Register, PIO_PSR); when the channel is configured as peripheral-driven, the pad output is enabled by a logic 0 state on the Peripheral Data Enable (EN_PERIPH_N) terminal. This signal originates from another on-chip peripheral. 6 PIO1 1321C-03/01 PIO1 Pin Signal Levels Each pin may be actively driven high or low, or its level may be determined by off-chip circuitry. The actual logic level on the pin is governed by the following conditions: * If a channel is driven by the PIO1 controller and is defined as an output (see "Output Enabling" above), its pin level is governed by the state of the Output Data Status Register (PIO_ODSR) which may be controlled by writing a logic 1 to the Set Output Data Control Register (PIO_SODR) or to the Clear Output Data Control Register (PIO_CODR). The programmed value may be read from the Output Data Status Register (PIO_ODSR). If a channel is driven by the PIO1 controller, but is not enabled as an output, the pin level will be determined by the external off-chip circuit, irrespective of the Output Data Status Register contents. If a channel is driven by an on-chip peripheral and the PIO Status Register (PIO_PSR) is programmed to enable the peripheral connection, its level will be defined by the peripheral. * * In all cases, the actual level on a pin may be monitored by reading the corresponding bit of the Pin Data Status Register (PIO_PDSR). Interrupts Each I/O channel can be programmed to generate an interrupt when a voltage level change occurs on the related external pin. Each individual channel may have its interrupt generation enabled or disabled according to the logic condition of the related bit in the Interrupt Mask Register (PIO_IMR), which is controlled by writing a logic 1 to the relevant bit of the Interrupt Enable (PIO_IER) or to the Interrupt Disable (PIO_IDR) Control Register, in the same fashion as for the other Control Registers described above. When a change in level occurs, the corresponding bit in the Interrupt Status Register (PIO_ISR) register is set, whether the pin is used for a peripheral function or for processor addressed PIO, and whether the channel is working in input or in output mode. When the Interrupt Status Register (PIO_ISR) is read by user software, its contents are automatically cleared. If the corresponding interrupt is enabled in the Interrupt Mask Register (PIO_IMR), the relevant interrupt signal is generated. The interrupt signals from all 32 channels are gated together to generate a single PIO Interrupt signal (PIO_INT) that is available for routing to the system interrupt controller. Glitch Filtering Optional glitch filtering is available for each channel. It is governed by the state of the Input Filter Status Register (PIO_IFSR) which is controlled by writing a logic 1 to the relevant bit of the Input Filter Enable (PIO_IFER) or to the Input Filter Disable (PIO_IFDR) Control Registers, in the same fashion as for the other control registers described above. Input glitch filtering may be selected, whether the pin is used for a peripheral function or for processor addressed parallel input. When the filter is activated, a glitch with a duration of less than 1/2 clock cycle is automatically rejected, while a pulse with a duration of 1 clock cycle or more is accepted. For pulse durations between 1/2 clock cycle and 1 clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 clock cycle. 7 1321C-03/01 Multi-driver (Open Drain) Each I/O can be programmed for multi-driver option. This means that the I/O is configured as open drain (can only drive a low level) in order to support external drivers on the same pin. An external pull-up is necessary to guarantee a logic level of one when the pin is not being driven. Registers PIO_MDER (Multi-driver Enable) and PIO_MDDR (Multi-driver Disable) control this option. Multi-driver can be selected whether the I/O pin is controlled by the PIO controller or the peripheral. PIO_MDSR (Multi-driver Status) indicates which pins are configured to support external drivers. 8 PIO1 1321C-03/01 PIO1 PIO1 User Interface Table 2. PIO1 Controller Memory Map Offset 0x00 0x04 0x08 Control Registers PIO Enable Register PIO Disable Register PIO Status Register Status Registers Name PIO_PER PIO_PDR PIO_PSR Access Write-only Write-only Read-only Reset State - - FFFFFFF (See Notes 1 and 4) 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 Multi-driver Enable Register Multi-driver Disable Register Interrupt Enable Register Interrupt Disable Register Set Output Data Register Clear Output Data Register Glitch Input Filter Enable Register Glitch Input Filter Disable Register Output Enable Register Output Disable Register Reserved PIO_OER PIO_ODR Output Status Register Reserved PIO_IFER PIO_IFDR Glitch Input Filter Status Register Reserved PIO_SODR PIO_CODR Output Data Status Register Pin Data Status Register PIO_ODSR PIO_PDSR PIO_IER PIO_IDR Interrupt Mask Register Interrupt Status Register PIO_IMR PIO_ISR PIO_MDER PIO_MDDR Write-only Write-only Read-only Read-only Write-only Write-only Read-only Read-only Write-only Write-only - - 0 (see Note 2) - - 0 0 (see Note 3) PIO_IFSR Write-only Write-only Read-only - - (See Note 4) PIO_OSR Write-only Write-only Read-only - - 0 0x58 Multi-driver Status Register PIO_MDSR Read-only (See Note 4) Notes: 1. Unless otherwise programmed during system-level design according to peripheral mapping and multiplexing. 2. The value of this register will depend on the level of the external pins. 3. This register is cleared on Reset. However, the first read of the register may give a non-zero value if any changes have occurred on any of the external pins between Reset and when the register is read. 4. The value of these registers can be customer-defined. The default value is 0. Reset Configuration The Reset state of the following PIO1 registers can be defined by the customer: PIO Status Filter, Glitch Input Filter Status, Multi-driver. 9 1321C-03/01 l User Interface Register Descriptions All control and status registers are 32-bit: each bit of the User Interface Registers is associated with the corresponding I/O channel, bit 0 with channel 0, bit 1 with channel 1, and so on. This mapping is shown diagrammatically in the table below. 31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 LPIO1/Peripheral Multiplexing PIO Enable Register Register Name: Access Type: PIO_PER Write-only For the bit configuration of the register, see "l User Interface Register Descriptions" above. This register is used to enable control of individual pins by the PIO controller rather than by an internally connected peripheral. When the PIO is enabled, the Data to Peripheral (D_TO_PERIPH) signal is held at logic zero. The register is programmed as follows: 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 0 = No effect. PIO Disable Register Register Name: Access Type: PIO_PDR Write-only This register is used to disable control of individual pins by the PIO controller. When PIO control is disabled, the peripheral function (if any) connected to the I/O channel is enabled to control the corresponding pin. The register is programmed as follows: 1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). 0 = No effect. PIO Status Register Register Name: Access Type: PIO_PSR Read-only Reset Value:FFFFFFF (Unless programmed otherwise in system level-design according to peripheral mapping and multiplexing) This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or disabled. The register reads as follows: 1 = PIO is active on the corresponding line (peripheral is inactive). 0 = PIO is inactive on the corresponding line (peripheral is active). 10 PIO1 1321C-03/01 PIO1 PIO Output Enable For the bit configuration of the register, see "l User Interface Register Descriptions" on page 10 PIO Output Enable Register Register Name: Access Type: PIO_OER Write-only This register is used to enable PIO output drivers. If the pin is driven by an internally connected peripheral, PIO_OER has no effect on the pin, but the information is stored. The register is programmed as follows: 1 = Enables the PIO output on the corresponding pin. 0 = No effect. PIO Output Disable Register Register Name: Access Type: PIO_ODR Write-only This register is used to disable PIO output drivers. If the pin is driven by an internally connected peripheral, PIO_ODR has no effect on the pin, but the information is stored. The register is programmed as follows: 1 = Disables the PIO output on the corresponding pin. 0 = No effect. PIO Output Status Register Register Name: Access Type: Reset Value: PIO_OSR Read-only 0 This register shows the PIO pin control (output enable) status which is programmed via PIO_OER and PIO_ODR. The defined value is effective only if the pin is controlled by the PIO. The register reads as follows: 1 = The corresponding PIO is output on this line. 0 = The corresponding PIO is input on this line. Glitch Filtering For the bit configuration of the register, see "l User Interface Register Descriptions" on page 10. PIO Input Filter Enable Register Register Name: Access Type: PIO_IFER Write-only This register is used to enable input glitch filters; it affects the data read from the pin whether or not the PIO is enabled. The register is programmed as follows: 1 = Enables the glitch filter on the corresponding pin. 0 = No effect. PIO Input Filter Disable Register Register Name: Access Type: IO_IFDR Write-only This register is used to disable input glitch filters. It affects the data read from the pin whether or not the PIO is enabled. The register is programmed as follows: 1 = Disables the glitch filter on the corresponding pin. 0 = No effect. 11 1321C-03/01 PIO Input Filter Status Register Register Name: Access Type: Reset Value: PIO_IFSR Read-only 0 This register indicates which pins have glitch filters selected, as programmed via PIO_IFER and PIO_IFDR. The register reads as follows: 1 = Filter is selected on the corresponding input (peripheral and PIO). 0 = Filter is not selected on the corresponding input. 12 PIO1 1321C-03/01 PIO1 PIO Data Output For the bit configuration of the register, see "l User Interface Register Descriptions" on page 10. PIO Set Output DataL Register Register Name: Access Type: PIO_SODR Write-only This register is used to set PIO data output to the corresponding pads. It affects the related pins only if the corresponding PIO outputs are enabled and if the pins are controlled by the PIO controller. Otherwise, the information is simply stored and is acted on if the PIO is later enabled. The register is programmed as follows: 1 = PIO output data on the corresponding pin is set (logic 1). 0 = No effect. PIO Clear Output Data Register Register Name: Access Type: PIO_CODR Write-only This register is used to clear PIO data output to the corresponding pads. It affects the related pins only if the corresponding PIO outputs are enabled and if the pins are controlled by the PIO controller. Otherwise, the information is simply stored and is acted on if the PIO is later enabled. The register is programmed as follows: 1 = PIO output data on the corresponding pin is cleared (logic 0). 0 = No effect. PIO Output Data Status Register Register Name: Access Type: Reset Value: PIO_ODSR Read-only 0 This register shows the output data status which is programmed via PIO_SODR or PIO_CODR. The bit pattern is effective only for those pins under the control of the PIO controller and only if the pins are enabled as outputs. Otherwise, the information is simply stored and is acted on if the PIO is later enabled. The register reads as follows: 1 = The output data for the corresponding pin is programmed to 1. 0 = The output data for the corresponding pin is programmed to 0. 13 1321C-03/01 Interrupt Masking For the bit configuration of the register, see "l User Interface Register Descriptions" on page 10. PIO Interrupt Enable Register Register Name: Access Type: PIO_IER Write-only This register is used to enable PIO interrupts generated by the corresponding pins; logic level changes are detected and stored in the Interrupt Status Register (PIO_ISR). Enabled interrupts will be generated whether the PIO is enabled or not. The register is programmed as follows: 1 = Enables an interrupt when a change of logic level is detected on the corresponding pin. 0 = No effect. PIO Interrupt Disable Register Register Name: Access Type: PIO_IDR Write-only This register is used to disable PIO interrupts generated by the corresponding pins. Logic level changes are still detected and stored in the Interrupt Status Register (PIO_ISR). Disabled interrupts will be inhibited whether the PIO is enabled or not. The register is programmed as follows: 1 = Disables the interrupt generated by the corresponding pin. 0 = No effect. PIO Interrupt Mask Register Register Name: Access Type: Reset Value: PIO_IMR Read-only 0 This register shows which pins have interrupts enabled. It is updated when interrupts are enabled or disabled by writing to PIO_IER or PIO_IDR. The register reads as follows: 1 = Interrupt is enabled from the corresponding pin. 0 = Interrupt is disabled from the corresponding input pin. 14 PIO1 1321C-03/01 PIO1 Interrupt Source For the bit configuration of the register, see "l User Interface Register Descriptions" on page 10. PIO Interrupt Status Register Register Name: Access Type: Reset Value: PIO_ISR Read-only 0 This register indicates, for each pin, when a logic level change has been detected (rising or falling edge). This is valid whether the PIO is selected for the pin or not and whether the pin is an input or output. The register is reset to zero following a read, as well as at reset. The register reads as follows: 1 = At least one change has been detected on the corresponding pin since the register was last read or since reset. 0 = No change has been detected on the corresponding pin since the register was last read or since reset. Output Pin Level For the bit configuration of the register, see "l User Interface Register Descriptions" on page 10. PIO Pin Data Status Register Register Name: Access Type: Reset Value: PIO_PDSR Read-only Undefined This register shows the logic level of the physical I/O pin. The pin logic levels are always valid, regardless of whether the pins are enabled as PIO, peripheral, input or output. The value of this register will depend on the level of the external pins. The register reads as follows: 1 = The corresponding pin is at logic 1. 0 = The corresponding pin is at logic 0. 15 1321C-03/01 Multi-drive Option For the bit configuration of the register, see "l User Interface Register Descriptions" on page 10. PIO Multi-Drive Enable Register Register Name: Access Type: PIO_MDER Write-only This register is used to enable PIO output drivers to be configured as open drain to support external drivers on the same pin. 1 = Enables multi-drive option on the corresponding pin. 0 = No effect. PIO Multi-drive Disable Register Register Name: Access Type: PIO_MDDR Write-only This register is used to disable the open drain configuration of the output buffer. 1 = Disables multi-drive option on the corresponding pin. 0 = No effect. PIO Multi-drive Status Register Register Name: Access Type: PIO_MDSR Read-only This register indicates which pins are configured with open drain drivers. 1 = PIO is configured as an open drain. 0 = PIO is not configured as an open drain. 16 PIO1 1321C-03/01 PIO1 Timing Diagrams Figure 4. APB Signal Timing p_stb p_stb_rising tSU_A p_a[13:0] tSU_DIN p_d_in[31:0] tSU_WRITE tHOLD_A tHOLD_DIN tHOLD_WRITE p_write tPD1 p_d_out[31:0] Valid tPD2 Figure 5. PIO Signal Timing clock tPD_PIO_INT PIO_int t PD_D_TO_PAD t PD_D_TO_PERIPH, t PD_OEN_TO_PAD d_to_pad d_to_periph oen_to_pad t t SU HOLD d_from_periph d_from_pad 17 1321C-03/01 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Atmel Rousset Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G75 0QR TEL (44) 1355-357-000 FAX (44) 1355-242-743 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex France TEL (33) 4-7658-3000 FAX (33) 4-7658-3480 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 (c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ARM7TDMI and AMBA are trademarks of ARM Limited. Terms and product names in this document may be trademarks of others Printed on recycled paper. 1321C-03/01/xM |
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